Can China actually train Kimi K3?

§1The question

Kimi K3 launched today: ~2.8T total parameters, 1M-token context, native multimodal, and a new hybrid linear attention scheme ("Kimi Delta Attention"). The tweet assumes a 2.8T-parameter model requires US-frontier-scale compute. This report runs the actual numbers: how much compute a K3-class run plausibly takes, what it costs on export-legal H800s, whether the constraint is FLOPs, interconnect, memory, or power, and whether Huawei's CloudMatrix superpods could carry the same run.

§2The training math you need

Five relations govern nearly everything below. They follow the roofline style of analysis Reiner Pope laid out on Dwarkesh's blackboard, plus two anchors every practitioner uses.

2.1 Training compute: the 6ND rule

Each token costs ~2 FLOPs per parameter forward and ~4 backward — but only over the active parameters. For a mixture-of-experts model, total parameter count is nearly irrelevant to compute; what you pay for is the slice of the network each token touches. This single fact does most of the work of answering the tweet. RL costs ~2–6·N·D per generated token (decode-heavy, lower utilization); serving costs 2·N·D.

The correction term is attention: F_attn/token ≈ (6–12)·L·h·S grows with sequence length S. At 4K context it is ~3–5% of the parameter FLOPs; at 1M it would be 6–12× them — which is why 1M-context models (a) need linear/sparse attention like KDA and (b) train almost all tokens at short context, with a staged extension at the end (K2: 15.5T tokens at 4K, only 60B at 32K; DeepSeek-V4 extends 4K → 16K → 64K → 1M). The 6ND rule therefore stays a good estimate of the bulk run.

2.2 What a chip actually delivers: MFU

Model FLOPs utilization is the fraction of peak the training loop sustains end-to-end. Frontier MoE runs on Hopper-class hardware sustain ~17–22% of FP8 peak (equivalently ~35–40% of BF16 peak) — we derive DeepSeek-V3's realized number below, and it anchors every estimate in this report.

2.3 The roofline: compute time vs. memory time

Per forward pass you must both do the math on active parameters and fetch all resident weights (plus KV state) from HBM. Equating the two sides gives the critical batch size ≈ 300 × sparsity (the ~300 is the FLOPs:memory-bandwidth ratio, roughly constant across GPU generations). Higher sparsity is nearly free compute-wise but demands bigger batches, more HBM capacity, and more interconnect — which is why sparsity, scale-up domain size, and memory co-evolve.

2.4 Interconnect: what expert parallelism demands

MoE layers route every token to experts scattered across GPUs — an all-to-all traffic pattern. Scale-up fabric (NVLink, in-rack) is ~8× faster than scale-out (NIC, cross-rack), so the all-to-all wants to stay inside the scale-up domain; whatever crosses nodes must fit through the NIC within the compute time it overlaps:

The DeepSeek-V4 report reduces this to one clean criterion. Per token-expert pair, an expert of hidden width d_e in a model of width h costs V_comp = 6·h·d_e FLOPs but moves only V_comm = 3h bytes (FP8 dispatch + BF16 combine). Expert count and top-k cancel from the ratio, so all-to-all can hide behind compute exactly when the chip's arithmetic intensity per byte of network clears 2·d_e:

Note the shape: the faster the chip and the narrower the expert, the more network each chip needs — a slower chip is actually easier to feed. At the V3-calibrated 343 useful TF/s, an H800 worst-cases to ~84 GB/s (d_e=2048) against a 50 GB/s NIC — which is exactly why DeepSeek invented node-limited routing and Moonshot keeps EP at 16: locality brings it under the line. An H20 at 50–148 TF/s needs only 8–24 GB/s (trivially fits); a B200 at ~1 PF/s needs ~160+ GB/s, which is why its expert parallelism lives inside the NVL72 scale-up domain. Nerfing NVLink (the H800's actual handicap) attacks exactly this term — and both DeepSeek and Moonshot's infrastructure papers are, at heart, engineering around it.

2.5 Memory ledger and power

A 2.8T-parameter model carries ~45 TB of sharded training state — a memory-capacity floor on cluster size (~600+ chips at 80 GB each just to hold state, more for activations). The last line is the power bound: at fixed site power P_IT, adding less-efficient chips cannot beat F/(P·η) — more chips only buy time while unused electrical and cooling capacity remains. Power cost, as we'll see, is economically trivial for a single run; power delivery (racks, cooling) is the real constraint on substituting many slow chips for few fast ones.

§3Two anchors: V3 and K2 were already trained on H800s

We don't need to speculate about whether frontier-quality training works on export-grade silicon — it's documented in two technical reports.

3.1 DeepSeek-V3: the cost table everyone cites

The systems work that made this possible on nerfed-interconnect hardware: FP8 mixed-precision GEMMs, the DualPipe schedule hiding all-to-all behind compute, ~20 SMs per GPU dedicated to communication, and node-limited routing (each token dispatched to ≤ 4 nodes) to economize the slow cross-node hop. DeepSeek's "suggestions to hardware vendors" section is a list of complaints about communication, not FLOPs.

3.2 Kimi K2: same playbook, one generation later

K2's sparsity scaling law is the strategic tell: holding active parameters fixed, Moonshot found more total experts monotonically improves quality — sparsity 48 saves 1.7× FLOPs vs sparsity 8 at equal loss. The gradient for a compute-constrained lab points exactly where K3 went: grow total parameters, hold active parameters down, spend the savings on tokens.

3.3 DeepSeek-V4-Pro: the third data point

DeepSeek's V4 report (arXiv:2606.19348, June 2026; cited here via the ChatGPT-Pro bottleneck analysis) extends the same lineage: 1.6T total / 49B active, 33T tokens ⇒ ~9.7×10²⁴ FLOPs, with context extended in stages 4K → 16K → 64K → 1M. Two systems findings matter for this report: it derives the C/B ≤ 2·d_e criterion of §2.4 and concludes interconnect no longer needs to grow with this design — and it reports that once fused kernels drive tensor cores, HBM, and network engines simultaneously, chip-level power throttling itself becomes a performance limiter. The bottleneck discourse has moved from "can the network keep up?" to "can the chip's power envelope?".

§4Sizing Kimi K3

Officially confirmed at launch: ~2.8T total parameters (largest open-weights model to date), 1M native context, native multimodal, and 896 experts with 16 active per token (~1.8% activation, under a scheme Moonshot calls "Stable LatentMoE" — the pre-launch rumor was exactly right). The attention stack is Kimi Delta Attention: per the published Kimi Linear paper (arXiv 2510.26692), three linear-attention KDA layers per full-attention layer, cutting KV cache up to 75% and delivering the headline 6.3× faster decoding at 1M context; "Attention Residuals" claim ~25% higher training efficiency at <2% extra cost. Weights ship in MXFP4 with MXFP8 activations. Still undisclosed: active parameters, token count, cluster, and cost.

4.1 Active parameters: the trunk formula

The clean way to size a MoE's active parameters (h/t the ChatGPT-Pro cross-check) splits the model into a trunk C that every token pays (attention, shared expert, embeddings) plus routed experts:

The blog's naive 16/896 × 2.8T ≈ 50.6B is the C=0 lower bound. Allowing C = 15–25B for a larger trunk, Attention Residuals, and native vision gives 65–75B: we take 70B active as central (60–80B as the interval — the same range the ChatGPT-Pro analysis lands on).

4.2 Tokens: what would a frontier data budget look like?

Moonshot has not disclosed the token count. Two reference points bracket it. The conservative one is lineage: K2 used 15.5T, DeepSeek-V4-Pro used 33T — so 20–35T is the "same-playbook" band. The aggressive one comes from the Reiner Pope / Dwarkesh lecture: working back from deployment economics (pretraining ≈ RL ≈ inference tokens at the cost-balanced optimum), Pope cites the rumor that current frontier models train on ~150T tokens, with ~100B active parameters — a deliberately speculative 6 × 100B × 150T ≈ 9×10²⁵ FLOPs frontier scenario. If K3's near-frontier benchmark position is taken at face value, the 150T-class data budget is the reading consistent with it, and Moonshot's rephrasing / synthetic-data pipeline (documented in the K2 report) is exactly the machinery you'd use to get there. We adopt 150T as the central scenario per this report's brief, keeping 20–30T rows as the conservative alternative.

4.3 The 2.5× efficiency claim

Kimi's launch blog states: "these structural changes yield an approximate 2.5× improvement in overall scaling efficiency compared to Kimi K2" (KDA + Attention Residuals + Stable LatentMoE). Read literally, that is a claim about converting FLOPs into capability, not about GPU throughput — so it does not reduce the 6ND bill; it multiplies what the bill buys. We report it as effective compute = 2.5 × physical FLOPs (K2-architecture-equivalent). Note the blog says MXFP4/MXFP8 quantization-aware training starts only at the SFT stage, so the bulk pretrain was not FP4-cheap.

§5The H800 budget

Apply the V3-anchored efficiency (343 sustained TFLOP/s per H800, i.e. 180K H800-hours per trillion tokens at 37B active, scaled by active parameters). This empirical number already absorbs bubbles, communication, and non-GEMM overheads for a V3-like short-context workload:

The conservative and moderate runs are DeepSeek-V3-class events: a mid-two-digit-million bill on a 10k-GPU cluster (even V3's own 2,048-GPU cluster could grind out the moderate run in ~7 months). The 150T central is a different animal — a ~$150M, ~3-month occupation of a 30k-H800 fleet — yet still: Moonshot has raised ~$3.9B, including a Jan 2026 $500M round explicitly earmarked for K3 compute, and was reportedly raising at a ~$31.5B valuation at launch. The run is ~4% of funds raised. For context, the H800s themselves (≈$1–2B of capex for 30–50k units at China market prices) dwarf the marginal cost of any single run — the fleet is the moat, the run is cheap. What the 150T scenario really prices is fleet size: it only fits a training season if Moonshot controls DeepSeek-scale (~50k Hopper-class) compute, which its funding implies it does.

§6What actually binds: chips, wires, memory, or watts?

6.1 FLOPs — not the bottleneck (and never were, per chip)

The H800 is H100 silicon: ~990 dense BF16 / ~1979 dense FP8 TFLOPs, 80 GB HBM3 at 3.35 TB/s — identical to the H100 SXM. Export rules cut its NVLink from 900 to 400 GB/s and its FP64 (34 → ~1 TFLOPs); neither touches transformer arithmetic. The tweet's chip list is also off: the H100 was never legally exportable — the actual sequence is A800/H800 (2022–Oct 2023), H20 (2024–Apr 2025 ban, licensed again mid-2025, ~1.46M installed), and since January 2026 the H200 (capped at 50% of US volumes with a 25% surcharge — likely the "few days ago" policy backdrop, alongside the May 2026 rule closing the offshore-Blackwell loophole). "66–92% fewer FLOPs/W than B200/B300" fits the H20, a deliberately compute-gutted inference part — not the H800 fleet these models train on, and per-chip FLOPs/W was never the binding term anyway: what binds is chips × time × engineering.

6.2 Interconnect — the real handicap, priced in engineering

Apply the §2.4 criterion to an H800 at the V3-calibrated 343 useful TF/s with K2-width experts (d_e = 2048): worst-case B_required = C/(2·d_e) ≈ 84 GB/s per chip — against a 50 GB/s NIC. Naively routed, the run is comms-bound. It fits only because of the tricks now standard in Chinese labs — all documented in the reports: DeepSeek's node-limited routing (each token confined to ≤4 of its 16 target slots cuts cross-node traffic ~4×, to ~21 GB/s sustained), 20 of 132 SMs dedicated to communication, DualPipe hiding the all-to-all (the V3 paper measures NVLink's effective 160 GB/s against InfiniBand's 50 GB/s — a 3.2× cliff every token must negotiate); Kimi's small EP=16, halved attention heads, and interleaved-1F1B overlap — and K3's launch material advertises "balanced expert-parallel training with static shapes and no host synchronization on the critical path," i.e. the 896-expert straggler problem got its own engineering. DeepSeek's "suggestions to hardware vendors" is explicit that burning SMs on communication "limits computational throughput" — the 400 GB/s NVLink cut costs real efficiency (V3's ~17% FP8 MFU vs ~25%+ achievable on full-NVLink hardware). Call it a 20–40% tax, not a wall — and note DeepSeek-V4's conclusion that with these designs, interconnect no longer needs to grow with the model.

6.3 Memory — a floor on cluster size, not a blocker

2.8T parameters ≈ 16.8 TB of BF16 weights + FP32 grad-accum (K2's recipe): 65.6 GB/GPU sharded over a 256-GPU model-parallel group, or 32.8 GB/GPU over 512 — feasible even on 96 GB H20s with ZeRO, recomputation, and K2-style CPU offload; ~45 TB all-in with master weights and Muon momentum. Gradient synchronization is equally tame: a 512-GPU group leaves a ~5.5B-parameter shard per rank, whose ~22 GB ring all-reduce takes ~0.4 s at 400G — hidden inside multi-second training steps on tens-of-millions-token batches. Practical floor: a few thousand GPUs for healthy activation headroom, comfortably below the 10k+ any such lab would use anyway. KDA is the memory-bandwidth play: linear attention holds per-token state constant, exactly the term (§2.3) that otherwise explodes at 1M context.

6.4 Power — economically irrelevant for the run

10k H800s draw ≈ 18 MW at ~1.4 kW/GPU all-in IT load (SemiAnalysis's H100-cluster figure) and PUE 1.3 — Chinese policy requires ≤1.25 for new large datacenters. The central run consumes ~20 GWh ≈ $1.2M at Chinese datacenter-hub rates (~$0.04–0.06/kWh vs ~$0.086 US industrial average) — about 5% of the rental cost, matching Epoch AI's finding that energy is 2–6% of frontier training cost. China added 429 GW of generation capacity in 2024 — roughly a third of the entire installed US grid — while US interconnection queues average ~5 years. Power constrains US buildouts, not an 18 MW Chinese training hall. The tweet's "way bigger power budgets" guess is true but backwards: power headroom is why aggregate Chinese compute can scale despite worse FLOPs/W silicon, but a single K3 run never gets near a power limit — and being ~30–40% cheaper on an input that is ~5% of run cost moves nothing.

Where power does bite is delivery density, not economics. Per Uptime Institute, 82% of operators run no racks above 30 kW, while four DGX-B200 boxes already draw ~57 kW in one rack — frontier campuses are purpose-built for densities ordinary datacenters can't host. And DeepSeek-V4 reports the same wall at chip level: with fused kernels driving tensor cores, HBM, and network engines at once, power throttling itself becomes the performance limiter. "Power is not the constraint" is true of the grid; it is decidedly not true of the rack or the die.

6.5 Can you substitute many slow chips for few fast ones?

The tweet's implicit question — and the H20 question — deserves its own answer. For the bulk 4–16K portion of MoE pretraining, the arithmetic says yes, nearly linearly: the §2.4 criterion shows a slower chip is easier to feed per chip (an H20 needs only 8–24 GB/s of all-to-all), its HBM and NVLink were never cut, and extra chips slot in through data and pipeline parallelism while expert-parallel groups stay local. The V4-Pro report makes the same point from the other side: interconnect stopped being the term that has to grow. The limits are physical and organizational:

• Power and racks scale with chip count: matching one B200 takes ~15.2 H20s at ~6.1× the GPU power (and ~5× the racks, NICs, switches). "5× slower, so buy 5× more" is only valid with ~5× the infrastructure — fine for a purpose-built Chinese AI campus with cheap power, ruinous in an ordinary colo.
• Long-context stages break data parallelism: a 94M-token global batch is ~23,000 independent 4K sequences but only 94 independent 1M sequences — at the final context-extension stage, extra chips must enter through context/pipeline parallelism, not more DP replicas.
• Reliability and iteration: a 100k-chip fleet fails constantly (checkpointing, replay, spares become first-order), and published "final-run" hours omit the research: DeepSeek states its V3 figure excludes all prior ablations. A US lab's real edge is running many candidate runs concurrently while a Chinese lab affords one.

So: H800 scaling is proven (V3, K2, and by every indication K3); H20 scaling is technically viable for pretraining but pays ~6× power per useful FLOP; the hard ceiling is neither FLOPs nor networking but power delivery, fleet reliability, and experiments-per-year.

6.6 Verdict table

§7The Huawei path: CloudMatrix superpods

Could K3 have been trained without Nvidia at all? On paper, nearly. The Ascend 910C delivers roughly 0.8 dense BF16 PFLOPs (about ⅓ of a B200, ~80% of an H800's BF16), and Huawei's CloudMatrix 384 supernode lashes 384 of them into one all-optical, fully peer-to-peer scale-up domain — more total FLOPs, HBM, and scale-up bandwidth than a GB200 NVL72, bought with ~4× the chips and ~2.3× the power per FLOP. For MoE all-to-all, a 384-chip scale-up domain is architecturally exactly what you want (§2.4): Huawei's answer to worse chips is a bigger, flatter network — and inside China, power and floor space are the cheap inputs.

A central-scenario K3 on 910Cs at a (generous) 20% BF16 MFU needs ~16M chip-hours of pretraining — e.g. ~40 CloudMatrix pods (15k chips, ~22 MW of pod power) for ~six weeks, or ~nine weeks with the RL phase. Feasible on paper; the binding constraints are upstream and organizational, not physical:

• HBM, not wafers: SMIC 7nm-class capacity (~45–60k wafers/month) is not the near-term limit — memory is. Each 910C needs 8 HBM stacks; China's ~13M-stack foreign stockpile (mostly Samsung HBM2E, bought before the Dec 2024 cutoff) supports ~1.6M packages and was expected to run out around end-2025. Domestic CXMT supply (~2M stacks in 2026) sustains only ~250–300k 910Cs per year on its own. SemiAnalysis counts ~805k Ascends shipped in 2025 (~653k of them 910C); Huawei's 2026 plan is ~600k 910Cs — large, but split across every Chinese cloud, and mostly on inference duty.
• No FP8, immature software: the 910C has no FP8 (it arrives with the Ascend 950), so DeepSeek/K3-style FP8 recipes don't port — and CANN vs. CUDA remains the widest gap. The FT reported DeepSeek spent months failing to complete an R2 training run on Ascend despite on-site Huawei engineers, then retreated to Nvidia for training while keeping Ascend for inference. Tellingly, DeepSeek's UE8M0 FP8 format and K3's own MXFP8/MXFP4 numerics both anticipate the FP8-capable domestic chips coming next.
• Roadmap: Atlas 950 SuperPoD (8,192 × Ascend 950DT, 8 EFLOPS FP8, Huawei's own in-house HBM at 4 TB/s) is slated for Q4 2026 — reportedly pulled forward to August on Huawei Cloud, with DeepSeek among the first adopters — and Atlas 960 (15,488 chips, 30 EFLOPS FP8) for Q4 2027. On paper these close most of the per-pod gap, with power-hunger as the accepted price — a trade China's grid can absorb. Beijing is forcing the transition regardless: since late 2025, state-funded datacenters are barred from foreign chips and major platforms were ordered to stop buying Nvidia.

There is meanwhile direct evidence the CloudMatrix system concept works for MoE serving: at EP=256, published CM384 tests sustain ~54 GB/s dispatch and ~103 GB/s combine per rank, and its 910C MLA kernels hit ~246 TF/s per die vs ~660 TF/s for the same kernel on H800 — the same utilization percentage on a much slower die, kept fed by the huge optical all-to-all domain. That validates Huawei's system-over-silicon approach for inference; it is not evidence K3 trained there.

Most likely reading of K3 specifically: pretrained on the existing Nvidia (H800-era) fleet with the K2 software stack; Ascend increasingly carries inference — Moonshot hasn't disclosed its infrastructure, and its provable lineage (K2) is H800. A full-Huawei frontier pretrain is plausible in 2026–27 but still carries schedule risk that a lab racing to a launch date avoids.

§9Answering the tweet

"How is a Chinese lab training a 3T model with orders of magnitude less compute?" Because a 3T-parameter MoE is not a 3T-compute model. At ~2.5% activation (70B of 2.8T), K3's pretraining is ~40× cheaper than the dense model the tweet is picturing: even on a frontier-rumor 150T-token data budget it is ~6×10²⁵ physical FLOPs — a GPT-4.5-class budget, roughly an eighth of the largest known run — executed as ~3 months on ~30k of the H800s China legally imported by the hundred thousand before October 2023; on a K2-style 20–30T budget it drops to ~10²⁵ and six weeks on 10k. Stack Kimi's claimed 2.5× architecture efficiency on top and the effective scale (~1.6×10²⁶ K2-equivalent) sits in the frontier band — which is exactly what its benchmarks show. The published Chinese systems innovations — extreme sparsity, FP8 pipelines, communication-hiding schedules, and now KDA/AttnRes — exist precisely to make that arithmetic work on nerfed interconnect.

Taking the tweet's hypotheses in order:

• "Huawei caught up big time" — partially. CloudMatrix 384 is a genuinely competitive system (1.7× an NVL72's dense BF16 by brute force), but HBM-capped 910C supply, missing FP8, and CANN software keep it mostly on inference duty in 2026 — DeepSeek demonstrably could not complete a frontier training run on it. K3 was almost certainly not pretrained on it.
• "Smuggled Blackwells" — real channel, unnecessary for this. Epoch estimates ~660k H100-equivalents smuggled through 2025, and Chinese subsidiaries acquired Blackwell-class chips offshore until the May 2026 rule closed that loophole; Alibaba and ByteDance also lease overseas Nvidia capacity. But Moonshot's provable lineage (K2) ran on legal H800s, and a K3-class budget simply doesn't require gray-market silicon.
• "Way bigger power budgets" — real but misaimed. Cheap abundant power (429 GW added in 2024, hub tariffs near $0.04–0.06/kWh) is why China can afford watt-hungry domestic silicon at fleet scale; a single training run is an ~18 MW, ~$1M-of-electricity event no grid notices. Energy is 2–6% of a frontier run's cost — a 40% discount on it buys ~2% of a run.
• "Kimi figured out training efficiency" — yes, and it's published. Muon (materially better token efficiency than AdamW, with QK-Clip making it stable at trillion-parameter scale), sparsity-48+ MoE scaling laws, KDA + Attention Residuals (~25% training-efficiency claim), rephrasing pipelines for token utility. None of it is mysterious; most of it is open-source.

Where the compute gap is real: aggregate capacity and its growth rate. The largest known run (Grok 4) is ~5×10²⁶ FLOPs — still ~8× our 150T central — and Epoch pegs US lab fleets at 1.7M H100-equivalents (OpenAI), >1M (Anthropic, on Trainium), 4–5M (Google), each headed to 5–6 GW during 2026; one analysis puts the US advantage in 2026-produced AI compute at 21–49×. More decisively, that surplus pours into RL post-training, reasoning-heavy serving, and — the quiet advantage — parallel experiments: published "final-run" hours exclude the ablations, and a lab with 10× compute runs 10 candidate architectures while its rival runs one. Export controls, on this evidence, impose an economic and iteration-speed tax rather than a feasibility ceiling: China's constraint shows up after pretraining, in RL scaling, long-thinking inference economics, experiments per year, and the ceiling on restocking trainers. That's the honest version of the tweet's concern — not whether Kimi can train K3, but whether anyone can serve and RL-scale it against B300 economics. Sparsity, ironically, is also the right hedge there: 16-of-896 experts is exactly what makes serving a 2.8T model on H20s and Ascends viable.

§10Sources & assumptions

1. DeepSeek-AI, "DeepSeek-V3 Technical Report," arXiv:2412.19437v2 — Table 1 (H800-hour budget), §3 (cluster, DualPipe, FP8, all-to-all engineering, hardware suggestions).
2. Kimi Team, "Kimi K2: Open Agentic Intelligence," arXiv:2507.20534v2 — §2.3–2.4 (architecture, sparsity scaling law, H800/RoCE cluster, parallelism and memory recipe), MuonClip.
3. Reiner Pope on the Dwarkesh Podcast (blackboard lecture) — roofline framing, critical batch ≈ 300×sparsity, scale-up:scale-out ≈ 8×, 6ND / 2–6ND / 2ND accounting, cost-equalization heuristics, and the ~150T-token / ~100B-active frontier rumor (explicitly flagged by Pope as rumor-grade) that anchors this report's central data budget.
4. DeepSeek-V4 report (arXiv:2606.19348, June 2026; read here via the ChatGPT-Pro analysis below) — DeepSeek-V4-Pro 1.6T/49B on 33T tokens; the C/B ≤ 2·d_e EP-communication criterion; staged context extension; chip-level power throttling as emerging limiter.
5. Kimi K3 launch blog (kimi.com/blog/kimi-k3): "these structural changes yield an approximate 2.5× improvement in overall scaling efficiency compared to Kimi K2"; MXFP4 weights / MXFP8 activations with quantization-aware training from the SFT stage onward; 16-of-896 expert activation.
6. Cross-check: a ChatGPT-Pro "Training Model Bottlenecks" analysis (July 2026) run on the same tweet — independent central estimate 70B active × 30T ≈ 1.3×10²⁵ FLOPs, same 343 TF/s V3 calibration, trunk formula for active parameters, H20-substitution bound (15.2 H20 ≈ 1 B200 at 6.1× GPU power), rack-density and reliability arguments. This report's conservative/moderate scenarios match it; the 150T central is deliberately more aggressive per the brief above.
7. Kimi K3 launch materials (July 16, 2026): 2.8T total, 1M context, 896 experts / 16 active ("Stable LatentMoE"), KDA + Attention Residuals, MXFP4/MXFP8, open weights promised July 27. KDA architecture: "Kimi Linear" (arXiv:2510.26692) — 3:1 KDA:MLA, ≤75% KV-cache reduction, ~6× decode at 1M. Active-parameter and token counts remain undisclosed and are this report's estimates, flagged as scenarios.
8. Chip specs: Nvidia datasheets and spec aggregations (H800/H100/H200/H20/A800/B200/B300); SemiAnalysis CloudMatrix 384 analysis (Apr 2025: 300 PF dense BF16, ~559 kW, 2.3–2.5× worse power/FLOP than GB200 NVL72) and Ascend production-ramp analysis (HBM stockpile ~13M stacks; 2025 output ~805k units); Huawei Atlas 950/960 announcements (Sept 2025). Where sources conflict, the calculator's data object carries the value used and can be edited live in the page source.
9. Export-control timeline: Oct 2022 controls → A800/H800 China SKUs → banned Oct 17, 2023; H20 license requirement Apr 2025, licensed resumption with 15% revenue share Jul–Aug 2025; H200 approved Jan 14, 2026 (50% volume cap, 25% surcharge); May 31, 2026 offshore-subsidiary rule; July 2026 congressional hearing ("trivial" H200 shipments) and Nvidia compliance whitelist.
10. Compute-ladder estimates: Epoch AI (GPT-4 2.1×10²⁵; GPT-4.5 ~6×10²⁵–10²⁶; GPT-5 ~5×10²⁵; Grok 4 ~5×10²⁶ ≈ 246M H100-hours, ~310 GWh, ~$490M; frontier compute growing 4–5×/yr). Fleet estimates (H100-equivalents, end-2025) and the ~660k-smuggled figure are also Epoch's. Energy share of training cost (2–6%) from Epoch's frontier-cost study; DeepSeek R2/Ascend reporting via FT.
11. Uncertainty: every output here is a roofline estimate with ~±30% error bars; K3 training internals are undisclosed as of launch day. Directional conclusions (§6, §9) survive the error bars.